The present invention relates to test and measurement of printed circuit boards, integrated circuits or multi-chip modules, and more particularly to a timing analyzer for embedded testing of such printed circuit boards, integrated circuits or multi-chip modules where the timing analyzer may be included in the end product.
As integrated circuits continue to increase in complexity and package density, designing for testability becomes necessary. One method of design for testability is a boundary scan test technique that has been developed by the Joint Test Action Group (JTAG) and is standardized in IEEE Standard 1149.1, which is incorporated herein by reference. The boundary scan test technique provides for embedded testing of integrated circuits and printed circuit boards. This technique was developed due to the difficulty of testing surface mount printed circuit boards. The high component density and fine lead sizes of surface mount components make testing using traditional bed-of-nails probes difficult at best. When the components are mounted on both sides of the board, or when circuit traces lie wholly on internal board layers, probing methods become inadequate. The boundary scan technique requires a four-wire serial test bus with four signals: Test Data In (TDI); Test Data Out (TDO); Test Mode Select (TMS); and Test Clock (TCK). TDI and TMS assume a logic high state if not actively driven, ensuring that the test circuitry always receives a known value on these lines. TDO is a three-state signal that is active when data is being shifted through an integrated circuit (IC) in which the hardware for this technique is embedded. At all other times it is a high impedance signal.
This technique allows the state of all digital I/O pins on a component to be examined or changed, hence the name "boundary scan." By wiring together the TMS and TCK on all ICs and connecting TDO of one IC to TDI of the next, the entire board is tested with a single bus. The details of this technique are described in the above-identified IEEE Standard 1149.1 and in an article in the Aug. 2, 1990 issue of EDN entitled "Adding Testability Also Aids Debugging" by Richard A. Quinnell, incorporated herein by reference. The circuitry defined by the boundary scan standard allows test instructions and associated test data to be fed into a component and, subsequently, allows the test results of execution of such instructions to be read out. All information, instructions, test data and test results, are communicated in a serial format.
Using this boundary scan technique allows virtual probing of state at the IC leads and provides an indication of whether the printed circuit board, integrated circuit or multi-chip module is properly connected. However the boundary scan technique does not identify where or what the problem may be when the printed circuit board, integrated circuit or multi-chip module is not functioning when the problem is related to speed or timing. Particularly where the malfunctioning is a result of timing errors within the printed circuit board or multi-chip module, there is no way to properly test the circuitry. Brooktree Corporation of San Diego, Calif., United States of America has developed a 200 MHZ ATE Channel Controller--the Bt612. The primary function of the Bt612 is for providing high-performance, on-the-fly per-pin timing and format, but it is also useful for central phase clock generation, both static and dynamic. The Bt612 is a low density, bipolar circuit with no program store, is expensive and uses excessive power. Further the vernier delay is an analog d.c. voltage that is proportional to the distance between clock pulses which is derived from a ramp signal.
What is needed is an inexpensive, highly integrated, multi-channel timing analyzer for embedded testing that tests timing signals for a printed circuit board, integrated circuit or multi-chip module.